1. Field of the Invention
The present disclosure herein relates to digital signal processing, and more particularly, to a dynamic circuit receiving as an input a slow signal.
2. Description of the Related Art
Semiconductor devices, and processors in particular, continue to decrease in size relative to the amount of data processed. As data speed and volume increase, it becomes challenging to keep power consumption of the semiconductor device low.
High-performance circuits may utilize dynamic circuitry to increase processing speed. System clocks have jitter, or variations in high or low levels, especially during rising and falling edges of the clock signal. While static circuitry may be affected by jitter, dynamic circuitry is not affected to the same extent. While static circuitry utilizes signals that are locked in at a rising (or falling) clock signal and held for a duration of a high or low clock period, dynamic circuitry allows a signal to rise or fall during a clock high (or low) period, and the signal is held until the next changing clock edge. For example, in the dynamic circuit if the input signal is low at a rising clock edge but changes to a high level during the high level of the clock, an output signal may be changed to high and held at a high level until the falling edge of the clock. Dynamic logic allows a circuit to operate with a higher processing speed, but may also consume more power than a static logic circuit.
One such semiconductor device is a cascode logic circuit having a MUX input. FIG. 1A illustrates a block diagram of a cascode logic circuit 100 having a MUX input. The cascode logic circuit 100 may include a pre-charge circuit 2 to pre-charge an output node. A logic unit 4 may receive inputs, perform a logic function, and output a signal to the cascode logic circuit output based on the logic function. An input unit 6 may receive at least one input and output a signal to the cascode logic circuit output based on the received input. Each of the logic unit 4 and input unit 6 may include at least one latch, 4a and 6a, connected to a clock signal to latch and hold an input signal value at a rising edge of the clock signal. A selection unit 8 may select one of the logic unit 4 and input unit 6 to output to the cascode logic circuit output.
FIG. 1B illustrates a schematic diagram of the cascode logic circuit in FIG. 1A. The pre-charge unit 2 corresponds to a transistor P1 having a source connected to a power source VDD and a gate connected to the clock signal CLK. When the CLK signal is low, the transistor P1 may pre-charge the node 21. NMOS transistors N1-N4 receive inputs A-D. When a select signal S and a clock signal CLK are high, transistors N6 and N8 are turned on, and the signals A-D input to the logic unit 4 are evaluated. In the example illustrated in FIG. 1B, if all of the transistors N1-N4 are turned on, the voltage at the node 21 is driven low, and the output Q is driven high, so that the logic unit acts as an AND gate. However, any configuration of transistors may be used to generate a desired logic function.
When the select signal S is low, transistor N7 is turned on, and input E is output. For example, if input E is high, transistor N5 is turned on, driving node 21 low and driving output Q high. Thus, the selection signal S acts as a MUX selection signal to determine which one of the logic inputs and the input E is output to the output of the cascode logic circuit.
Since the cascode logic circuit 100 receives input signals of static circuits, the signals A-E and S must be held by latches L1-L6 for the duration of a high CLK signal. The latches take up circuit space and may also contribute to a circuit delay. In addition, since all of the logic unit 4, the selection transistor N6 and the clock transistor N8 are located on a path between power VDD and ground, they may all contribute to a signal delay. Specifically, since resistance and capacitance in an electrical path contribute to signal delay, each transistor adds resistance to the signal path.
A cascode logic circuit 100 may malfunction if the inputs A-E are static inputs on the critical path and the input E is a slow input on a non-critical path. A critical path is defined as a path in which the path delay comprises a high percentage of a clock cycle, such as 80%-90% of a clock cycle. A “critical” input signal is an input signal along the critical path.
A “slow” input is defined as an input having a delay greater than a delay of the clock signal CLK. The above definition of a “slow” input is applied throughout the specification and claims. For example, if a delay of the input E causes the input signal E to enter the latch L5 after a clock CLK rising edge has passed, then the input E will delay operation of the cascode logic circuit 100 by a clock cycle.